SVNews r318496

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2017-05-18 21:00:50 - r318496 by marius (Marius Strobl)

Complete list of files affected by revision r318496:

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   Contents     MODIFY   /stable/11  
  History   Contents   Diff   MODIFY   /stable/11/sys/dev/sdhci/sdhci_acpi.c  
  History   Contents   Diff   MODIFY   /stable/11/sys/dev/sdhci/sdhci_pci.c  

Commit message:

MFC: r318282

- Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail
  and Braswell eMMC and SDXC controllers share the same IDs. Like in
  the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ
  quirk (see r311794 for the corresponding change to the sdhci(4) PCI
  PCI front-end), though. However, due to the shared ACPI IDs, this
  is trickier to do.
- Intel Apollo Lake eMMC and SDXC controllers are affected by the
  APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May
  Lead to Unpredictable System Behavior") silicon bug. When this
  erratum hits, typically both SDHCI and XHCI controllers wedge.
  According to Intel, using ADMA2 with 64-bit addressing and 96-bit
  descriptors serves as a workaround. Until such times when sdhci(4)
  has ADMA2 support, flag DMA as broken for affected interfaces.
  This turns out to work around the problem, too, at the cost of
- In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC
  and SDXC controllers, too.


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